The present invention relates to calibrating a direct conversion receiver, and more particularly to an apparatus and method for feeding an internal calibration signal through an electro-static discharge protection circuitry for a direct conversion receiver.
The basic principle of a superheterodyne receiver is to convert a band of RF signals to an intermediate frequency (IF) by mixing a first tunable local oscillator (LO) signal with the RF signals, and further convert the IF signals to a baseband frequency by mixing a second LO signal with the IF signals. A direct conversion receiver (DCR) is a receiver that directly converts RF signals to the baseband frequency in a single conversion step, without having to first convert the RF signals to an intermediate frequency. In a direct conversion receiver the LO signal is set to the same frequency as the desired RF channel, which means that the intermediate frequency is zero, or Direct Current (DC). Direct conversion receivers therefore require less external circuitry than other receivers and have the added advantages of lightweight and low cost.
A DCR has the well-known problem of DC offset associated with the process of down-converting the RF signal, however, which may initially be small but is amplified during signal processing, as the signal will pass through at least one gain stage. This amplified DC offset can cause saturation of the signal, at best decreasing sensitivity of the receiver, and at worst causing the receiver to fail. DC offset can also be created if there is leakage of the local oscillator signal to the front-end RF input. This can affect the linearity of the receiver. The less linear the front-end receiver is, the more the local oscillation signal will be affected by interference.
If the DCR is calibrated, the level of DC offset inherent in a received RF signal can be accurately measured, stored, and used to compensate for DC offset in future operations. Some receivers employ a method of external calibration for this purpose, which requires external circuitry, therefore negating the advantages the DCR has of simple circuitry. To solve this problem, a related art DCR uses a process of internal calibration, whereby an internal calibration signal is generated for adjusting DC offset of received signals.
Please refer to FIG. 1. FIG. 1 is a diagram of a related art DCR 10 that uses internal calibration. Please note that the diagram is a simplified diagram and only shows the essential parts. The DCR 10 comprises a front-end input stage 20 for receiving an RF signal, further comprising an antenna 22 for receiving the RF signal, a filter 24 for filtering the received RF signal, and a low noise amplifier 26, for amplifying the filtered RF signal; an internal signal generator 30, for generating a calibration signal; and a switch unit 40, selectively coupled to the internal signal generator 30 and the front-end input stage 20, for allowing the calibration signal to be fed to an input node of a processing unit 52 when the switch unit 40 is in the ‘on’ position and for disconnecting the internal signal generator 30 from the front-end input stage 20 when the DCR 10 is operating in normal mode.
When the DCR 10 is in calibration mode, i.e. the switch unit 40 is turned on and the calibration signal is passed to the processing unit 52, the DC offset can be correctly calculated through following signal processing. When the switch unit 40 is turned off, although the switch unit 40 is not operational, the direct coupling of the switch unit 40 to the front-end input stage 20 will cause some parasitic resistance and parasitic capacitance to be present in the DCR 10. The parasitic resistance introduces thermal noise into the circuit, which greatly affects the noise performance of the circuit and changes the receiver characteristics. The parasitic capacitance affects the input matching condition of the front-end circuit. The performance of the related art DCR 10 is thus degraded.